Invention Publication
- Patent Title: ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES
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Application No.: US18106350Application Date: 2023-02-06
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Publication No.: US20230187447A1Publication Date: 2023-06-15
- Inventor: Yu-Chang LIN , Chun-Feng NIEH , Huicheng CHANG , Hou-Yu CHEN , Yong-Yan LU
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- The original application number of the division: US14859165 2015.09.18
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/66 ; H01L21/265 ; H01L21/8234 ; H01L21/8238 ; H01L21/02 ; H01L27/12 ; H01L21/84 ; H01L29/49

Abstract:
A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
Public/Granted literature
- US12021082B2 Enhanced channel strain to reduce contact resistance in NMOS FET devices Public/Granted day:2024-06-25
Information query
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