Invention Publication
- Patent Title: Multigate Device Having Reduced Contact Resistivity
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Application No.: US18175221Application Date: 2023-02-27
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Publication No.: US20230215928A1Publication Date: 2023-07-06
- Inventor: Georgios Vellianitis , Blandine Duriez
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/8234 ; H01L29/417 ; H01L29/66 ; H01L29/786 ; H01L29/06

Abstract:
An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10−9 Ω-cm2.
Public/Granted literature
- US12080771B2 Multigate device having reduced contact resistivity Public/Granted day:2024-09-03
Information query
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