Invention Publication
- Patent Title: TREATING MULTIPLE CACHE LINES AS A MERGED CACHE LINE TO STORE MULTIPLE BLOCKS OF DATA
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Application No.: US17729233Application Date: 2022-04-26
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Publication No.: US20230342298A1Publication Date: 2023-10-26
- Inventor: Vladimir VASEKIN , David Michael BULL , Vincent REZARD , Anton ANTONOV
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Main IPC: G06F12/0842
- IPC: G06F12/0842 ; G06F12/0891 ; G06F9/38

Abstract:
Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.
Public/Granted literature
- US11947460B2 Treating multiple cache lines as a merged cache line to store multiple blocks of data Public/Granted day:2024-04-02
Information query
IPC分类: