Invention Application
- Patent Title: PRE-FLOW OF P-TYPE DOPANT PRECURSOR TO ENABLE THINNER P-GAN LAYERS IN GALLIUM NITRIDE-BASED TRANSISTORS
-
Application No.: US17519429Application Date: 2021-11-04
-
Publication No.: US20230132548A1Publication Date: 2023-05-04
- Inventor: Atsunori Tanaka , Sanyam Bajaj , Michael S. Beumer , Robert Ehlert , Gregory P. McNerney , Nicholas Minutillo , Johann C. Rode , Suresh Vishwanath , Patrick M. Wallace
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/20 ; H01L29/66
Abstract:
In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.
Information query
IPC分类:
