Invention Publication
- Patent Title: BACK-END-OF-LINE 2D TRANSISTOR
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Application No.: US17855620Application Date: 2022-06-30
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Publication No.: US20240006521A1Publication Date: 2024-01-04
- Inventor: Chia-Ching LIN , Shriram SHIVARAMAN , Kevin P. O'BRIEN , Ashish Verma PENUMATCHA , Chelsey DOROW , Kirby MAXEY , Carl H. NAYLOR , Sudarat LEE , Uygar E. AVCI
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/775
- IPC: H01L29/775 ; H01L27/12 ; H01L29/78 ; H01L29/40 ; H01L29/66 ; H01L29/417
Abstract:
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.
Information query
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