Invention Publication
- Patent Title: PROGRAMMABLE LOGIC BLOCK WITH MULTIPLE TYPES OF PROGRAMMABLE ARRAYS AND FLEXIBLE CLOCK SELECTION
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Application No.: US17861067Application Date: 2022-07-08
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Publication No.: US20240014819A1Publication Date: 2024-01-11
- Inventor: Mark WALLIS , Jean-Francois LINK , Joran PANTEL
- Applicant: STMICROELECTRONICS (ROUSSET) SAS
- Applicant Address: FR Rousset
- Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee Address: FR Rousset
- Main IPC: H03K19/17724
- IPC: H03K19/17724 ; H03K19/17736 ; H03K19/173 ; H03K19/20

Abstract:
An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.
Public/Granted literature
- US11942935B2 Programmable logic block with multiple types of programmable arrays and flexible clock selection Public/Granted day:2024-03-26
Information query
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