A memory control circuit and a refresh method for a dynamic random access memory (DRAM) array are provided. The memory control circuit includes a mode register circuit, a command decoder and a refresh circuit. The mode register circuit includes a plurality of mode registers. The command decoder receives a refresh command and sets a flag of a target mode register corresponding to the refresh command among the plurality of mode registers to a setting value. The refresh circuit refreshes the DRAM array in response to the refresh command through the command decoder and the setting value of the flag of the target mode register.