Invention Publication
- Patent Title: METHODS AND APPARATUS TO REDUCE RETIMER LATENCY AND JITTER
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Application No.: US17956487Application Date: 2022-09-29
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Publication No.: US20240113851A1Publication Date: 2024-04-04
- Inventor: Ani Xavier , Jagannathan Venkataraman
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.
Public/Granted literature
- US11956340B1 Methods and apparatus to reduce retimer latency and jitter Public/Granted day:2024-04-09
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