Invention Publication
- Patent Title: MEMORY COHERENCE PROTOCOL FOR COMMUNICATING DATA ASSOCIATED WITH A SHARED STATE BETWEEN PROCESSOR CORES
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Application No.: US17974881Application Date: 2022-10-27
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Publication No.: US20240143506A1Publication Date: 2024-05-02
- Inventor: Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Main IPC: G06F12/0817
- IPC: G06F12/0817 ; G06F3/06

Abstract:
A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory line in a shared state.
Public/Granted literature
- US12292832B2 Memory coherence protocol for communicating data associated with a shared state between processor cores Public/Granted day:2025-05-06
Information query
IPC分类: