A memory device includes a memory cell array including a plurality of memory cells coupled to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation based on a weighted access count on the memory cell array, a register configured to store a weighted access count for each of a plurality of row addresses; an accumulator configured to accumulate a current weighted access count corresponding to an access spacing to the weighted access count stored in the register, and a calculator configured to calculate the access spacing.