A hardware mechanism capable of performing state saving and restoring operations, for use in a computer environment having a computer system having a central processor unit (CPU) with one or more data buses, a set of general purpose registers, instruction decoding logic and a mechanism for detecting interrupt conditions. The present invention generates new SAVE and RESTORE control signals and additional memory elements temporarily store the contents of the general purpose registers during interrupt conditions. The hardware mechanism includes an input section for transferring information from the one or more data buses to general purpose registers for storing the information. An output section is used for transferring the stored information from the general purpose registers to the data bus(es). A set of shadow latches store the contents of the general purpose registers when the CPU issues the SAVE control signal and transfer the contents back to the general purpose registers when the CPU issues the RESTORE control signal.