Invention Grant
US06365506B1 Dual-damascene process with porous low-K dielectric material 有权
双镶嵌工艺与多孔低K电介质材料

  • Patent Title: Dual-damascene process with porous low-K dielectric material
  • Patent Title (中): 双镶嵌工艺与多孔低K电介质材料
  • Application No.: US09859762
    Application Date: 2001-05-17
  • Publication No.: US06365506B1
    Publication Date: 2002-04-02
  • Inventor: Chih-Han ChangHsin-Chuan Tsai
  • Applicant: Chih-Han ChangHsin-Chuan Tsai
  • Priority: TW89125098 20001127
  • Main IPC: H01L214763
  • IPC: H01L214763
Dual-damascene process with porous low-K dielectric material
Abstract:
This invention relates to a dual damascene process with porous low-k dielectric material. A first insulating layer is formed on a porous low-k dielectric layer. The first insulating layer has a first pattern for defining a first opening in the low-k dielectric layer. Also, the invention includes the step of forming a second insulating layer on the first insulating layer. Both the first insulating layer and the second insulating layer are used as a hard mask, the two insulating layers being of different materials. The second insulating layer has a second pattern for defining a second opening in the low-k dielectric layer. Then, at least one etch is performed to form a dual damascene structure in the porous low-k dielectric layer by the different insulating layers which cause different protection time in etching the porous low-k dielectric layer.
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