Invention Grant
- Patent Title: Circuit package and method of plating the same
- Patent Title (中): 电路封装及其电镀方法
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Application No.: US10674370Application Date: 2003-09-30
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Publication No.: US07019394B2Publication Date: 2006-03-28
- Inventor: Xiaowei Yao , Tam Nguyen , Marc Finot , Rickie C. Lake , Jeffrey A. Bennett , Robert Kohler
- Applicant: Xiaowei Yao , Tam Nguyen , Marc Finot , Rickie C. Lake , Jeffrey A. Bennett , Robert Kohler
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Marshall, Gerstein & Borun LLP
- Main IPC: H01L23/053
- IPC: H01L23/053

Abstract:
A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
Public/Granted literature
- US20050077609A1 Circuit package and method of plating the same Public/Granted day:2005-04-14
Information query
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