Invention Grant
- Patent Title: Routing vias in a substrate from bypass capacitor pads
- Patent Title (中): 从旁路电容器衬垫的衬底中路由通孔
-
Application No.: US10940100Application Date: 2004-09-14
-
Publication No.: US07075185B2Publication Date: 2006-07-11
- Inventor: Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Gary Taylor , David Quint
- Applicant: Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Gary Taylor , David Quint
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.
Public/Granted literature
- US20060055049A1 Routing vias in a substrate from bypass capacitor pads Public/Granted day:2006-03-16
Information query
IPC分类: