Invention Grant
- Patent Title: Wiring substrate and electronic parts packaging structure
- Patent Title (中): 接线基板和电子零件包装结构
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Application No.: US10709096Application Date: 2004-04-13
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Publication No.: US07183647B2Publication Date: 2007-02-27
- Inventor: Kei Murayama , Masahiro Sunohara
- Applicant: Kei Murayama , Masahiro Sunohara
- Applicant Address: JP Nagano
- Assignee: Shinko Electric Industries, Co., Ltd.
- Current Assignee: Shinko Electric Industries, Co., Ltd.
- Current Assignee Address: JP Nagano
- Agency: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP
- Priority: JP2003-120499 20030424
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.
Public/Granted literature
- US20040212087A1 WIRING SUBSTRATE AND ELECTRONIC PARTS PACKAGING STRUCTURE Public/Granted day:2004-10-28
Information query
IPC分类:
