Invention Grant
US07227921B2 Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
有权
锁相环（PLL）电路，用于选择性地校正不同模式下的时钟偏移
- Patent Title: Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
- Patent Title (中): 锁相环（PLL）电路，用于选择性地校正不同模式下的时钟偏移
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Application No.: US10379776Application Date: 2003-03-03
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Publication No.: US07227921B2Publication Date: 2007-06-05
- Inventor: Jim Butler , Raul Oteyza
- Applicant: Jim Butler , Raul Oteyza
- Applicant Address: US CA Costa Mesa
- Assignee: Emulex Design & Manufacturing Corporation
- Current Assignee: Emulex Design & Manufacturing Corporation
- Current Assignee Address: US CA Costa Mesa
- Agency: Morrison & Foerster LLP
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H03L7/06
Abstract:
A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.
Public/Granted literature
- US20030156674A1 Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes Public/Granted day:2003-08-21
Information query
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