Invention Grant
US07256107B2 Damascene process for use in fabricating semiconductor structures having micro/nano gaps
有权
用于制造具有微/纳米间隙的半导体结构的镶嵌工艺
- Patent Title: Damascene process for use in fabricating semiconductor structures having micro/nano gaps
- Patent Title (中): 用于制造具有微/纳米间隙的半导体结构的镶嵌工艺
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Application No.: US11121690Application Date: 2005-05-03
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Publication No.: US07256107B2Publication Date: 2007-08-14
- Inventor: Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
- Applicant: Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
- Applicant Address: US CA Oakland
- Assignee: The Regents of the University of California
- Current Assignee: The Regents of the University of California
- Current Assignee Address: US CA Oakland
- Agent John P. O'Banion; Henry K. Woodward
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L21/78 ; H01L21/301
Abstract:
In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
Public/Granted literature
- US20050250236A1 Damascene process for use in fabricating semiconductor structures having micro/nano gaps Public/Granted day:2005-11-10
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