Invention Grant
- Patent Title: Method of manufacturing a multilayer printed wiring board
- Patent Title (中): 制造多层印刷线路板的方法
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Application No.: US11210860Application Date: 2005-08-25
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Publication No.: US07363706B2Publication Date: 2008-04-29
- Inventor: Eiji Hirata
- Applicant: Eiji Hirata
- Applicant Address: JP Tokyo
- Assignee: CMK Corporation
- Current Assignee: CMK Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- Priority: JP2004-376564 20041227
- Main IPC: H01K3/10
- IPC: H01K3/10 ; H05K1/14 ; H05K1/11

Abstract:
This invention provides a multilayer printed wiring board having flat via holes. This is a multilayer printed wiring board formed by alternately laminating multiple metal foils and insulating layers, in which an interlayer connection via pad provided in a first insulating layer, a wiring circuit and an interlayer connection via bottom pad of a second insulating layer are provided in the same surface layer and at least the interlayer connection via pad and the interlayer connection via bottom pad of the second insulating layer have the same thickness.
Public/Granted literature
- US20060137904A1 Multilayer printed wiring board and method of manufacturing the same Public/Granted day:2006-06-29
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