Invention Grant
US07368974B2 Signal adder circuit capable of removing effects due to phase error or amplitude error of I and Q signals
失效
信号加法器电路能够消除由于I和Q信号的相位误差或振幅误差引起的影响
- Patent Title: Signal adder circuit capable of removing effects due to phase error or amplitude error of I and Q signals
- Patent Title (中): 信号加法器电路能够消除由于I和Q信号的相位误差或振幅误差引起的影响
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Application No.: US11479742Application Date: 2006-06-30
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Publication No.: US07368974B2Publication Date: 2008-05-06
- Inventor: Takeo Suzuki , Shigeru Osada
- Applicant: Takeo Suzuki , Shigeru Osada
- Applicant Address: JP Tokyo
- Assignee: Alps Electric Co., Ltd.
- Current Assignee: Alps Electric Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Beyer Law Group LLP
- Priority: JP2005-251187 20050831
- Main IPC: G06F7/44
- IPC: G06F7/44

Abstract:
A signal adder circuit includes: an adding unit that includes at least a pair of amplification elements in which a constant current flows between ground terminals and a ground, input signals having different phases are input to input terminals, and output terminals to which a power supply voltage is applied are connected to each other; a gain control unit that is provided between the ground and each of the ground terminals of the amplification elements so as to adjust the amplitudes of the input signals having different phases; and a phase control unit that is provided between the ground and each of the ground terminals of the amplification elements so as to adjust the phases of the input signals having different phases.
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