Invention Grant
US07444493B2 Address translation for input/output devices using hierarchical translation tables
有权
使用分层转换表的输入/输出设备的地址转换
- Patent Title: Address translation for input/output devices using hierarchical translation tables
- Patent Title (中): 使用分层转换表的输入/输出设备的地址转换
-
Application No.: US10956198Application Date: 2004-09-30
-
Publication No.: US07444493B2Publication Date: 2008-10-28
- Inventor: Ioannis Schoinas , Rajesh Madukkarumakumana , Gilbert Neiger , Richard Uhlig , Ku-jei King
- Applicant: Ioannis Schoinas , Rajesh Madukkarumakumana , Gilbert Neiger , Richard Uhlig , Ku-jei King
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00
Abstract:
An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.
Public/Granted literature
- US20060075146A1 Address translation for input/output devices using hierarchical translation tables Public/Granted day:2006-04-06
Information query
