Invention Grant
- Patent Title: Solder interconnection array with optimal mechanical integrity
- Patent Title (中): 具有最佳机械完整性的焊接互连阵列
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Application No.: US10711501Application Date: 2004-09-22
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Publication No.: US07445141B2Publication Date: 2008-11-04
- Inventor: Glenn G. Daves , David L. Edwards , Mukta G. Farooq , Frank L. Pompeo
- Applicant: Glenn G. Daves , David L. Edwards , Mukta G. Farooq , Frank L. Pompeo
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: DeLio & Peterson, LLC
- Agent Kelly M. Nowak; Wenjie Li
- Main IPC: B23K31/02
- IPC: B23K31/02

Abstract:
A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.
Public/Granted literature
- US20060060636A1 SOLDER INTERCONNECTION ARRAY WITH OPTIMAL MECHANICAL INTEGRITY Public/Granted day:2006-03-23
Information query
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