Invention Grant
- Patent Title: Method of fabricating a high-layer-count backplane
- Patent Title (中): 制造高层计数背板的方法
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Application No.: US11537754Application Date: 2006-10-02
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Publication No.: US07448132B2Publication Date: 2008-11-11
- Inventor: Joel R. Goergen
- Applicant: Joel R. Goergen
- Applicant Address: US CA San Jose
- Assignee: Force10 Networks, Inc.
- Current Assignee: Force10 Networks, Inc.
- Current Assignee Address: US CA San Jose
- Agent James E. Harris
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low- noise high-power distribution layers in a single mechanically stable board.
Public/Granted literature
- US20070039171A1 Method of Fabricating a High-Layer-Count Backplane Public/Granted day:2007-02-22
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