Invention Grant
US07626234B2 Semiconductor device with shallow trench isolation and its manufacture method
失效
具有浅沟槽隔离的半导体器件及其制造方法
- Patent Title: Semiconductor device with shallow trench isolation and its manufacture method
- Patent Title (中): 具有浅沟槽隔离的半导体器件及其制造方法
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Application No.: US11429962Application Date: 2006-05-09
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Publication No.: US07626234B2Publication Date: 2009-12-01
- Inventor: Kengo Inoue , Hiroyuki Ota
- Applicant: Kengo Inoue , Hiroyuki Ota
- Applicant Address: JP Tokyo
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Tokyo
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2004-060210 20040304
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.
Public/Granted literature
- US20060255426A1 Semiconductor device with shallow trench isolation and its manufacture method Public/Granted day:2006-11-16
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