Invention Grant
US07642146B2 Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
有权
具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏
- Patent Title: Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
- Patent Title (中): 具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏
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Application No.: US11620447Application Date: 2007-01-05
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Publication No.: US07642146B2Publication Date: 2010-01-05
- Inventor: James Joseph Chambers , Mark Robert Visokay , Luigi Colombo
- Applicant: James Joseph Chambers , Mark Robert Visokay , Luigi Colombo
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/8238
- IPC: H01L21/8238
Abstract:
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
Public/Granted literature
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