Invention Grant
US07642572B2 Integrated circuit having a memory cell array and method of forming an integrated circuit
失效
具有存储单元阵列的集成电路和形成集成电路的方法
- Patent Title: Integrated circuit having a memory cell array and method of forming an integrated circuit
- Patent Title (中): 具有存储单元阵列的集成电路和形成集成电路的方法
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Application No.: US11735164Application Date: 2007-04-13
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Publication No.: US07642572B2Publication Date: 2010-01-05
- Inventor: Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
- Applicant: Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
- Applicant Address: DE Munich
- Assignee: Qimonda AG
- Current Assignee: Qimonda AG
- Current Assignee Address: DE Munich
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
Public/Granted literature
- US20080253160A1 INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT Public/Granted day:2008-10-16
Information query
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