Invention Grant
- Patent Title: Semiconductor device with reduced fringe capacitance
- Patent Title (中): 具有降低的边缘电容的半导体器件
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Application No.: US11823892Application Date: 2007-06-29
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Publication No.: US07642603B2Publication Date: 2010-01-05
- Inventor: Suman Datta , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
- Applicant: Suman Datta , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119
Abstract:
In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.
Public/Granted literature
- US20090001474A1 Semiconductor device with reduced fringe capacitance Public/Granted day:2009-01-01
Information query
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