Invention Grant
US07642808B2 Impedance adjusting circuit and semiconductor memory device having the same
失效
阻抗调整电路和具有该阻抗调整电路的半导体存储器件
- Patent Title: Impedance adjusting circuit and semiconductor memory device having the same
- Patent Title (中): 阻抗调整电路和具有该阻抗调整电路的半导体存储器件
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Application No.: US12005905Application Date: 2007-12-28
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Publication No.: US07642808B2Publication Date: 2010-01-05
- Inventor: Chun-Seok Jeong , Kang-Seol Lee
- Applicant: Chun-Seok Jeong , Kang-Seol Lee
- Applicant Address: KR Kyoungki-Do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-Do
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Priority: KR10-2007-0063312 20070626
- Main IPC: H03K19/003
- IPC: H03K19/003
Abstract:
An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration resistor circuit and generate a second calibration code, the second calibration resistor circuit being connected to a first node; and a transmission line circuit configured to be responsive to a control signal to connect the first node to a pin of a system employing the impedance adjusting circuit.
Public/Granted literature
- US20090002018A1 Impedance adjusting circuit and semiconductor memory device having the same Public/Granted day:2009-01-01
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