Invention Grant
US07642823B2 Semiconductor memory device including delay-locked-loop control circuit and control method for effective current consumption management 有权
半导体存储器件包括延迟锁定环控制电路和有效消耗电流管理的控制方法

  • Patent Title: Semiconductor memory device including delay-locked-loop control circuit and control method for effective current consumption management
  • Patent Title (中): 半导体存储器件包括延迟锁定环控制电路和有效消耗电流管理的控制方法
  • Application No.: US12174000
    Application Date: 2008-07-16
  • Publication No.: US07642823B2
    Publication Date: 2010-01-05
  • Inventor: Kwang Jun Cho
  • Applicant: Kwang Jun Cho
  • Applicant Address: KR Kyoungki-do
  • Assignee: Hynix Semiconductor Inc.
  • Current Assignee: Hynix Semiconductor Inc.
  • Current Assignee Address: KR Kyoungki-do
  • Agency: Ladas & Parry LLP
  • Priority: KR10-2006-0096613 20060929
  • Main IPC: H03L7/06
  • IPC: H03L7/06
Semiconductor memory device including delay-locked-loop control circuit and control method for effective current consumption management
Abstract:
A delay-locked-loop control circuit and a method of controlling a delay-locked-loop. When the delay-locked-loop is in an off-operation mode, such as a power-down mode, a self-refresh emulation mode, a self-refresh mode, and the like, the delay-locked-loop is updated with a predetermined period, thereby preventing a malfunction of the delay-locked-loop. The delay-locked-loop has an oscillating portion which generates an oscillation signal having a predetermined period when in an OFF state; a pulse generating portion which generates a pulse signal having a predetermined period using the oscillation signal; a dividing portion which divides the pulse signal to generate a delay-locked-loop update signal; and a combining portion which combines the delay-locked-loop update signal and a delay-locked-loop on signal that is enabled by an external command to generate a delay-locked-loop control signal for controlling the delay-locked-loop.
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