Invention Grant
- Patent Title: DLL circuit and test method thereof
- Patent Title (中): DLL电路及其测试方法
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Application No.: US11588403Application Date: 2006-10-27
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Publication No.: US07642825B2Publication Date: 2010-01-05
- Inventor: Kouji Maeda
- Applicant: Kouji Maeda
- Applicant Address: JP Kawasaki, Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kawasaki, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2005-312495 20051027
- Main IPC: H03L7/26
- IPC: H03L7/26

Abstract:
A DLL circuit includes a first delay line circuit, a first phase comparison circuit, a control circuit, and a first selecting circuit. The first delay line circuit can change a delay amount and provide a delay to a first clock signal. The first phase comparison circuit can detect a phase difference between the first clock signal and an output signal of the first delay line circuit, and a phase difference between a test clock signal of which frequency is lower than the first clock signal and an output signal of the first delay line circuit or a signal after dividing the output signal. The control circuit controls a delay amount of the first delay line circuit according to the detection result of the first phase comparison circuit.
Public/Granted literature
- US20070096785A1 DLL circuit and test method thereof Public/Granted day:2007-05-03
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