An NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistance memory element 10 via the NMOS transistor 14 to switch the resistance memory element 10 from the low resistance state to the high resistance state, the gate voltage of the NMOS transistor 14 is set at a value which is equal to or greater than the total of the reset voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14 and is smaller than the total of the set voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14, whereby the voltage applied to the resistance memory element 10 is set at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.