Invention Grant
- Patent Title: Method of design analysis of existing integrated circuits
- Patent Title (中): 现有集成电路设计分析方法
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Application No.: US10929798Application Date: 2004-08-31
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Publication No.: US07643665B2Publication Date: 2010-01-05
- Inventor: Vyacheslav L. Zavadsky , Val Gont , Edward Keyes , Jason Abt , Stephen Begg
- Applicant: Vyacheslav L. Zavadsky , Val Gont , Edward Keyes , Jason Abt , Stephen Begg
- Applicant Address: CA
- Assignee: Semiconductor Insights Inc.
- Current Assignee: Semiconductor Insights Inc.
- Current Assignee Address: CA
- Agency: Price, Heneveld, Cooper, DeWitt & Litton, LLP
- Main IPC: G06K9/00
- IPC: G06K9/00

Abstract:
The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
Public/Granted literature
- US20060045325A1 Method of design analysis of existing integrated circuits Public/Granted day:2006-03-02
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