Invention Grant
- Patent Title: Device and method for configuring a cache tag in accordance with burst length
- Patent Title (中): 根据突发长度配置缓存标签的设备和方法
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Application No.: US11499108Application Date: 2006-08-03
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Publication No.: US07644235B2Publication Date: 2010-01-05
- Inventor: Joseph T. Pawlowski
- Applicant: Joseph T. Pawlowski
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: G06F13/00
- IPC: G06F13/00

Abstract:
In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not functioning properly. In addition, the burst length of the SRAM is increased to reduce the number of tag subarrays necessary for operation of the cache tag so any nonfunctional tag subarrays are no longer necessary. In accordance with the indications from the programmed laser fuses and the increased burst length, logic circuitry disables any nonfunctional tag subarrays, leaving only functional tag subarrays to provide tag functionality for the memory cache. As a result, an SRAM that is typically scrapped as a result of nonfunctional tag subarrays can, instead, be recovered for sale and subsequent use.
Public/Granted literature
- US20060271816A1 Device and method for configuring a cache tag in accordance with burst length Public/Granted day:2006-11-30
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