Invention Grant
US07644248B2 Mechanism to generate logically dedicated read and write channels in a memory controller
有权
在存储器控制器中产生逻辑专用读和写通道的机制
- Patent Title: Mechanism to generate logically dedicated read and write channels in a memory controller
- Patent Title (中): 在存储器控制器中产生逻辑专用读和写通道的机制
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Application No.: US11528774Application Date: 2006-09-27
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Publication No.: US07644248B2Publication Date: 2010-01-05
- Inventor: Ramesh Subashchandrabose , Anupam Mohanty , Rajat Agarwal
- Applicant: Ramesh Subashchandrabose , Anupam Mohanty , Rajat Agarwal
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F13/00
- IPC: G06F13/00
Abstract:
According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.
Public/Granted literature
- US20080077761A1 Mechanism to generate logically dedicated read and write channels in a memory controller Public/Granted day:2008-03-27
Information query
