Invention Grant
- Patent Title: Method for analyzing circuits having MOS devices
- Patent Title (中): 用于分析具有MOS器件的电路的方法
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Application No.: US11433960Application Date: 2006-05-15
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Publication No.: US07644380B1Publication Date: 2010-01-05
- Inventor: Manish Pandey , Samuel L. Kerner , Chih-chang Lin
- Applicant: Manish Pandey , Samuel L. Kerner , Chih-chang Lin
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Method for analyzing a circuit composed of MOS devices. The method can be used to direct MOS devices in static and dynamic circuits and involves identifying an undirected MOS device that connects nets. Functions of the nets that cause each net to be logic values are defined as a function of inputs to the circuit. The defined functions can include pulldown functions or both pullup and pulldown functions. A set of rules is used to determine the direction of a signal that flows through a device and applies defined functions. The rules for analyzing static devices may differ from the rules for analyzing dynamic devices. Devices that are determined to have uni-directional signal flow can be directed. Additionally, devices having bi-directional signal flow and uni-directional observability can be directed.
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