Invention Grant
US07645634B2 Method of fabricating module having stacked chip scale semiconductor packages
有权
制造具有堆叠芯片级半导体封装的模块的方法
- Patent Title: Method of fabricating module having stacked chip scale semiconductor packages
- Patent Title (中): 制造具有堆叠芯片级半导体封装的模块的方法
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Application No.: US12125770Application Date: 2008-05-22
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Publication No.: US07645634B2Publication Date: 2010-01-12
- Inventor: Marcos Karnezos
- Applicant: Marcos Karnezos
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/02
Abstract:
Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire bonding between the first and second package substrates.
Public/Granted literature
- US20080220563A1 MODULE HAVING STACKED CHIP SCALE SEMICONDUCTOR PACKAGES Public/Granted day:2008-09-11
Information query
IPC分类:
