Invention Grant
US07645673B1 Method for generating a deep N-well pattern for an integrated circuit design 有权
用于生成用于集成电路设计的深N阱图案的方法

  • Patent Title: Method for generating a deep N-well pattern for an integrated circuit design
  • Patent Title (中): 用于生成用于集成电路设计的深N阱图案的方法
  • Application No.: US10772029
    Application Date: 2004-02-03
  • Publication No.: US07645673B1
    Publication Date: 2010-01-12
  • Inventor: Michael PelhamJames Burr
  • Applicant: Michael PelhamJames Burr
  • Main IPC: H01L21/336
  • IPC: H01L21/336 G06F17/50
Method for generating a deep N-well pattern for an integrated circuit design
Abstract:
A method for the design and layout for a patterned deep N-well. A Tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.
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