Disclosed is a method of manufacturing an isolation layer pattern in a semiconductor device and an isolation layer pattern in a semiconductor device. A device at a low voltage device formation region may be substantially immune to electric fields from a high voltage device formation region. A field insulation film pattern in a low voltage device formation region (e.g. a logic region) may implement a relatively small design rule at an isolation layer pattern. A method of manufacturing an isolation layer pattern in a semiconductor device (e.g. which may embody a device relatively immune to an electric field from a high voltage device formation region) may include field insulation film patterns with a relatively small design rule in a low voltage device formation region (e.g. a logic region).