Invention Grant
- Patent Title: Method for forming a dual interlayer dielectric layer of a semiconductor device
- Patent Title (中): 形成半导体器件的双层介电层的方法
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Application No.: US11644890Application Date: 2006-12-26
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Publication No.: US07645697B2Publication Date: 2010-01-12
- Inventor: Tae Young Lee
- Applicant: Tae Young Lee
- Applicant Address: KR Seoul
- Assignee: Dongbu Electronics Co., Ltd.
- Current Assignee: Dongbu Electronics Co., Ltd.
- Current Assignee Address: KR Seoul
- Agent Andrew C. Sonu
- Priority: KR10-2005-0134182 20051229
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method for forming a dual interlayer dielectric layer, which is capable of preventing an interlayer delamination phenomenon generated between an etch stop layer and an interlayer dielectric layer is provided. An interlayer dielectric layer of a dual structure is formed such that a first interlayer dielectric layer and a second interlayer dielectric layer are sequentially stacked on the etch stop layer. The etch stop layer is formed on a substrate, the substrate having a source/drain region and a gate formed therein. The dual interlayer dielectric layer is selectively etched, and a conductive material is deposited thereon, thereby forming a contact. The O3-TEOS layer and the PE-TEOS layer used as the first interlayer dielectric layer can relieve a compressive stress and improve adhesion force, respectively, thereby preventing the interlayer delamination phenomenon.
Public/Granted literature
- US20070155162A1 Method for forming a dual interlayer dielectric layer of a semiconductor device Public/Granted day:2007-07-05
Information query
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