Invention Grant
- Patent Title: Manufacturing method of silicon wafer
- Patent Title (中): 硅晶片的制造方法
-
Application No.: US10562236Application Date: 2004-10-28
-
Publication No.: US07645702B2Publication Date: 2010-01-12
- Inventor: Sakae Koyata , Kazushige Takaishi
- Applicant: Sakae Koyata , Kazushige Takaishi
- Applicant Address: JP Tokyo
- Assignee: SUMCO Corporation
- Current Assignee: SUMCO Corporation
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2003-401657 20031201
- International Application: PCT/JP2004/016001 WO 20041028
- International Announcement: WO2005/055301 WO 20050616
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
The manufacturing method of the present invention provides a silicon wafer, both sides of the wafer having a highly accurate flatness and small surface roughness, which is a single surface mirror-polished wafer with the front and rear surfaces of the wafer identifiable by visual observation, and excellent in flatness when held by a stepper chuck and the like. The manufacturing method of the present invention includes an etching process, a lapping process, and a double surface polishing process to simultaneously polish the front and rear surfaces of a wafer after the etching process. The polishing removal depth (A) of the wafer front surface is 5 to 10 μm in the double surface simultaneous polishing process, and the polishing removal depth (B) in the rear surface is 2 to 6 μm, and a difference between the polishing removal depth A and the polishing removal depth B is 3 to 4 μm.
Public/Granted literature
- US20070119817A1 Manufacturing method of silicon wafer Public/Granted day:2007-05-31
Information query
IPC分类: