An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132). The switching circuit (130) include a first positive feedback loop including a first internal feedback transistor (MN1) that reinforces a signal level at the first control node (131) and a second positive feedback loop including a second internal feedback transistor (MN2) that reinforces a signal level at the second control node 132. An output stage (140) has at least one input coupled to receive at least one output signal from the switching circuit (130) and provide at least one translated output supplying the higher logic-level voltage range signal.