A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.