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US07646649B2 Memory device with programmable receivers to improve performance 有权
具有可编程接收器的存储器件,以提高性能

Memory device with programmable receivers to improve performance
Abstract:
A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.
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