Invention Grant
- Patent Title: Instruction-associated processor resource optimization
- Patent Title (中): 指令关联处理器资源优化
-
Application No.: US11540910Application Date: 2006-09-28
-
Publication No.: US07647487B2Publication Date: 2010-01-12
- Inventor: Bran Ferren , W. Daniel Hillis , Nathan P. Myhrvold , Clarence T. Tegreene , Lowell L. Wood, Jr.
- Applicant: Bran Ferren , W. Daniel Hillis , Nathan P. Myhrvold , Clarence T. Tegreene , Lowell L. Wood, Jr.
- Applicant Address: US WA Bellevue
- Assignee: Searete, LLC
- Current Assignee: Searete, LLC
- Current Assignee Address: US WA Bellevue
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F15/00

Abstract:
Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.
Public/Granted literature
- US20070050556A1 Multiprocessor resource optimization Public/Granted day:2007-03-01
Information query