Invention Grant
- Patent Title: Manufacturing method of mask and optimization method of mask bias
- Patent Title (中): 掩模的制造方法和掩模偏差的优化方法
-
Application No.: US11779968Application Date: 2007-07-19
-
Publication No.: US07647568B2Publication Date: 2010-01-12
- Inventor: Jun Seok Lee
- Applicant: Jun Seok Lee
- Applicant Address: KR Seoul
- Assignee: Dongbu Hitek Co., Ltd.
- Current Assignee: Dongbu Hitek Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Saliwanchik, Lloyd & Saliwanchik
- Priority: KR10-2006-0068698 20060721
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
In a fabrication method of a semiconductor device a manufacturing method of a mask and an optimization method of a mask bias incorporating an optical proximity correction are provided. The manufacturing method of the mask incorporating an optical proximity correction can form a pattern in an excellent quality in a dense area where a micro design pattern in an irregular array state is formed. Also, a desired design pattern can be formed using a mask according to embodiments of the present invention regardless of an array state.
Public/Granted literature
- US20080022256A1 Manufacturing Method of Mask and Optimization Method of Mask Bias Public/Granted day:2008-01-24
Information query