Invention Grant
US07647571B1 Method of identifying state nodes at the transistor level in a sequential digital circuit
有权
在顺序数字电路中识别晶体管级的状态节点的方法
- Patent Title: Method of identifying state nodes at the transistor level in a sequential digital circuit
- Patent Title (中): 在顺序数字电路中识别晶体管级的状态节点的方法
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Application No.: US11729153Application Date: 2007-03-28
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Publication No.: US07647571B1Publication Date: 2010-01-12
- Inventor: Tathagato Rai Dastidar , Amir Yashfe , Partha Ray
- Applicant: Tathagato Rai Dastidar , Amir Yashfe , Partha Ray
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Mark C. Pickering
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.
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