Invention Grant
US07647572B1 Managing formal verification complexity of designs with multiple related counters
有权
用多个相关计数器管理设计的正式验证复杂性
- Patent Title: Managing formal verification complexity of designs with multiple related counters
- Patent Title (中): 用多个相关计数器管理设计的正式验证复杂性
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Application No.: US11851330Application Date: 2007-09-06
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Publication No.: US07647572B1Publication Date: 2010-01-12
- Inventor: Chung-Wah Norris Ip , Lawrence Loh , Vigyan Singhal , Howard Wong-Toi
- Applicant: Chung-Wah Norris Ip , Lawrence Loh , Vigyan Singhal , Howard Wong-Toi
- Applicant Address: US CA Mountain View
- Assignee: Jasper Design Automation, Inc.
- Current Assignee: Jasper Design Automation, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45
Abstract:
A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.
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