Invention Grant
- Patent Title: Method of forming fuse region in semiconductor damascene process
- Patent Title (中): 半导体镶嵌工艺中形成熔丝区域的方法
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Application No.: US11616270Application Date: 2006-12-26
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Publication No.: US07648870B2Publication Date: 2010-01-19
- Inventor: Se Yeul Bae
- Applicant: Se Yeul Bae
- Applicant Address: KR Seoul
- Assignee: Dongbu HiTek Co., Ltd.
- Current Assignee: Dongbu HiTek Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Sherr & Vaughn, PLLC
- Priority: KR10-2005-0131010 20051227
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is deposited over the first conductive layer. A second conductive layer is buried in the interlayer dielectric layer by a dual damascene process to simultaneously form an interconnection and a fuse. The resultant structure is coated with a passivation layer. The fuse is cut to form a severed portion. A selective metal layer is deposited over the severed portion.
Public/Granted literature
- US20070148956A1 METHOD OF FORMING FUSE REGION IN SEMICONDUCTOR DAMASCENE PROCESS Public/Granted day:2007-06-28
Information query
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