Methods for forming DRAM devices including protective patterns and related devices

Invention Grant

US07648875B2 Methods for forming DRAM devices including protective patterns and related devices 失效

Title translation: 用于形成包括保护图案和相关装置的DRAM装置的方法

Please log in to see more content

Patent Title: Methods for forming DRAM devices including protective patterns and related devices
Patent Title (中): 用于形成包括保护图案和相关装置的DRAM装置的方法
Application No.: US11327067

Application Date: 2006-01-06
Publication No.: US07648875B2

Publication Date: 2010-01-19
Inventor: Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
Applicant: Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
Applicant Address: KR
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR
Agency: Myers Bigel Sibley & Sajovec, P.A.
Priority: KR10-2005-0001307 20050106
Main IPC: H01L21/8242
IPC: H01L21/8242

Methods for forming DRAM devices including protective patterns and related devices

Abstract:

A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.

Abstract(Chinese):

在半导体衬底上形成第一层间电介质。接触焊盘被形成为通过第一层间电介质接触衬底。在第一层间电介质上形成位线不接触接触垫。形成第二层间电介质并将其平坦化以暴露位线的顶部。在所得结构的整个表面上形成保护层。在保护层上形成牺牲层。牺牲层，保护层和第二层间电介质在两个相邻的位线之间被图案化以形成露出接触焊盘的底部电极接触孔。形成导电层并平坦化以形成填充底部电极接触孔的底部电极接触塞。

Public/Granted literature

US20060146595A1 Methods for forming DRAM devices including protective patterns and related devices Public/Granted day:2006-07-06

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）