Invention Grant
US07648885B2 Method for forming misalignment inspection mark and method for manufacturing semiconductor device
失效
用于形成不对准检查标记的方法和用于制造半导体器件的方法
- Patent Title: Method for forming misalignment inspection mark and method for manufacturing semiconductor device
- Patent Title (中): 用于形成不对准检查标记的方法和用于制造半导体器件的方法
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Application No.: US11491302Application Date: 2006-07-24
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Publication No.: US07648885B2Publication Date: 2010-01-19
- Inventor: Takashi Sato
- Applicant: Takashi Sato
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-214201 20050725
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
A method for forming a misalignment inspection mark is disclosed. The formation method includes forming a reference layer device pattern and a first mark in a reference layer and forming an overlying layer device pattern and a second mark in a layer over the reference layer, the overlying layer device pattern corresponding to the reference layer. The second mark is formed by forming a second mark area adjacent to the first mark, the second mark area including an arrangement of a plurality of patterns having a line width, a pitch, and a pattern density at least one of which is equivalent to that of the overlying layer device pattern, and removing those of the plurality of patterns which are arranged at boundaries of the second mark area.
Public/Granted literature
- US20070026543A1 Method for forming misalignment inspection mark and method for manufacturing semiconductor device Public/Granted day:2007-02-01
Information query
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