Invention Grant
- Patent Title: Method to fabricate gate electrodes
- Patent Title (中): 制造栅电极的方法
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Application No.: US12033487Application Date: 2008-02-19
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Publication No.: US07648898B2Publication Date: 2010-01-19
- Inventor: Srinivasa R. Banna
- Applicant: Srinivasa R. Banna
- Applicant Address: US CA Los Gatos
- Assignee: DSM Solutions, Inc.
- Current Assignee: DSM Solutions, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Baker Botts L.L.P.
- Main IPC: H01L21/3205
- IPC: H01L21/3205

Abstract:
A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of nitride to the first layer of oxide. The method further comprises depositing a second layer of oxide and planarizing the oxide to expose at least a portion of the layer of nitride. The method further comprises stripping at least a portion of the layer of nitride to create one or more notches and removing at least a portion of the first layer of oxide. The method further comprises depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into at least one of the one or more notches.
Public/Granted literature
- US20090206336A1 Method to fabricate gate electrodes Public/Granted day:2009-08-20
Information query
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